In this paper, a simple and efficient clock boosting mechanism to increase the performance of an adaptive router in NETWORK-on-CHIP ((NOC)) is proposed. One of the most serious disadvantages of a fully adaptive wormhole router is performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits. The simulation results show that the proposed clock boosting mechanism enhances the performance of the original adaptive router by increasing the accepted load and decreasing the average latency in the region of effective bandwidth. The enhanced throughput of a router results in power saving by reducing the operating frequency of a router for certain communication bandwidth requirements.

NETWORK on-CHIP is a communication subsystem within an integrated circuit that provides communication between processors in the on-CHIP system. There are several different ways to get from one node to another. Therefore, there must be a routing algorithm to find the route to the destination. This paper presents an algorithm based on the reduction of the passing path to reach a packet from origin to destination which is able to increase the reliability, reduce latency, power consumption and increase NETWORK efficiency on the CHIP. And this is when most of the fault-tolerant NETWORKs presented in this field increase parameters such as delay, power consumption and circuit complexity in order to achieve higher reliability. The proposed method improves NETWORK performance with minimal hardware changes and circuit complexity. The path passed by the packet is reduced to reach the destination, which means passing through fewer links and routers and less chance of encountering faulty links and routers and increasing NETWORK reliability. Also, passing fewer links and routers will reduce NETWORK latency and power consumption.

The performance of NETWORKs-on-CHIP is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D NETWORKs-on-CHIP. In 3D integrated circuits, different devices are stacked through silicon via in which the vertical connections are vulnerable to manufacturing process variations. Therefore, because of the high impact of faulty links or nodes on the performance of a NETWORK-on-CHIP, utilizing a fault-tolerant routing algorithm is of great importance especially for 3D NETWORKs-on-CHIP in which the vertical links are more vulnerable. In this paper, a new fault-tolerant routing algorithm called FT-ZXY is proposed to be used in 3D NETWORKs-on-CHIP. This routing method is capable of tolerating multiple vertical faulty links in addition to single horizontal faulty links without using any virtual channels thus incurs a very low hardware overhead. Experimental results reveal that the proposed routing algorithm has more reliability compared to the previous designs while incurs less latency and requires lower area and power overheads.

In NETWORK-on-CHIP architecture, wired structure and multi-step communication increase consumption power and latency. Combining wired media for a regular transmission and high-bandwidth wireless media for multi-step communication is a way to reduce latency and consumption of power. Wireless nodes are prone to error in on-CHIP wireless NETWORKs due to their complexity and relatively high usage; they are also crowded due to their sharing between several nodes, but their job is to increase efficiency. However, the presence of wireless nodes in wireless NETWORKs on the CHIP increases the cost and area. Therefore, finding an optimal structure for communication between cores is necessary. In this paper, a new three-dimensional architecture for a Wireless NETWORK on CHIP is presented, which has two levels; depending on the location of the error in the second level, the wireless routers in the first level are assigned to the processing elements. The demand matrix is used to optimize different traffic patterns. The performance of 3D architecture has been compared under different traffic patterns. The obtained results show that the proposed structure has a relatively good performance and increases the NETWORK's reliability.

It is undeniable that scheduling plays an important role in increasing the NETWORK quality on CHIP. If experts realize the significant of mapping and scheduling in getting rid of delays and increasing performance of these systems, they will ponder over these activities much more scrupulously. The operation scheduling problem in NETWORK on CHIP ((NOC)) is NP-hard; therefore, effective heuristic methods are needed to provide modal solutions. In this paper, ant colony scheduling was introduced as a simple and effective method to increase allocator matching efficiency and hence NETWORK performance, particularly suited to NETWORKs with complex topology and asymmetric traffic patterns. The proposed algorithm was studied in torus and flattened-butterfly topologies with multiple types of traffic pattern. For evaluating the performance of the proposed algorithm, specialized simulator NETWORK on CHIP entitled by BookSim working under Linux operation system was used. Evaluation results showed that this algorithm, in many causes, had positive effects on reducing NETWORK delays and increasing CHIP performance compared with other algorithms. For instance, for a complex topologies, this algorithm under maximum injection_rate of up to (10%) increasing throughput have been observed, injection rate, on average, compared to other existing algorithms.

By increasing, the complexity of CHIPs and integrating more components into a CHIP has made NETWORK – on-CHIP known as an important infrastructure for NETWORK communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of CHIPs, the possibility of fault in the CHIP NETWORK increases and providing correction and fault tolerance methods is one of the principles of today's CHIP design. Faults may have undesirable effects on the correct system operation and system performance. In this paper the communication infrastructure fault has been considered as same as link and router fault and the fault tolerance low cost routing algorithm has been suggested base on local fault information By using quad neighbor fault information to avoid back tracking in routing in order to select possible minimal path to destination. In this article, we have suggested cost aware fault tolerance (CAFT) routing algorithm. Our contribution in this algorithm is minimum local fault information, minimum routing decision overhead by implementing routing logic base and determining shortest possible path. For deadlock freedom using an additional virtual channel along Y dimension and prohibiting certain routing turns. In order to evaluate the performance of our routing, we compared it with other fault tolerant routing in terms of average packet latency, throughput and power.

Due to increasing number of cores, the placement of the cores in (NOC) platform has become an important issue. If we can map the application cores close to each other to place them with more communication requirements, the performance parameters will improve and the NETWORK will be more efficient. In this paper, we propose two low complexity heuristic algorithms for the application mapping onto (NOC) to improve latency. In addition, one approach has been proposed to extract an Abstract graph from an application core graph, so, using this resent approach, we can map applications in two proposed algorithms. Moreover, we use bypass routers that can route packets in a cycle from the source to destination. Proposed algorithms and previous papers were compared on two real applications VOPD and MPEG-4 and results were reported.